Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell holds a certain level of a given physical quantity such as an electrical charge or voltage, which represents the data stored in the cell. The levels of this physical quantity are also referred to as storage values or analog values. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a programming state that represents one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, stores two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Various methods for programming and erasing analog memory cells are known in the art. Some memory devices use an iterative programming and verification (P&V) process that applies a sequence of pulses to a group of memory cells and verifies the programmed values during the sequence.
Various techniques are known in the art for protecting data in memory devices against failures. For example, U.S. Pat. No. 5,533,190, whose disclosure is incorporated herein by reference, discloses a method for assuring consistency between data and parity in a disk array system following a reset or a power failure condition which interrupts the execution of write I/O operations. The method includes the steps of: examining drive activities to identify unfinished write I/O operations due to an interrupt condition; logging information necessary to identify the unfinished operations and the array redundancy groups associated with the unfinished operations into a non-volatile memory; and checking for log entries in the non-volatile memory during a disk array subsystem initialization or the restoration of power. For each unfinished operation identified in the log, the method further includes the steps of: performing a bit-wise exclusive-OR of corresponding portions of the data stored within the associated redundancy group to calculate parity consistent therewith; and writing the calculated parity to the parity storage areas within the associated redundancy group. For an array operating with a failed disk drive member (i.e., in degraded mode), the method also logs information necessary to identify the storage areas to which the unfinished write I/O operations map new data and parity, and some form of the old data and parity information saved to that storage areas to which the unfinished write I/O operations map new data and parity. Following the system reset, or restoration of power, consistent parity is determined for each associated redundancy group.
U.S. Pat. No. 7,487,394, whose disclosure is incorporated herein by reference, discloses a method in which data associated with the state of a parity update operation in a disk array system such as a RAID-6 system is stored during performance of the operation so that, in the event the operation is interrupted, recovery may be initiated using the stored data. The stored data may include a state indicator that is indicative of the status of the parity update operation, and snapshot data (e.g., a delta value indicative of a difference between new and old data) captured during the parity update operation.